FPGA-based Hardware Software Co -design to Accelerate Brain Tumour Segmentation

被引:0
|
作者
Rayapati, Vinay [1 ]
Gogireddy, Ravi Kiran Reddy [1 ]
Gandi, Ajay Kumar [1 ]
Gajawada, Saketh [1 ]
Sanampudi, Gopala Krishna Reddy [1 ]
Rao, Nanditha [1 ]
机构
[1] Int Inst Informat Technol Bangalore, Bangalore, India
关键词
Terms Brain tumour segmentation; FPGA; Hardware software co-design; Accelerator;
D O I
10.1109/ISCAS58744.2024.10558230
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Brain tumors are a major concern, being the leading cause of cancer-related deaths. Computer-aided diagnosis significantly reduces the workload on physicians and improves cancer diagnosis and treatment. Brain tumor segmentation is a computationally intensive image-processing task. In this paper, we propose an FPGA-based Hardware-Software Co-design to accelerate this task using Watershed and Otsu thresholding algorithms. The FPGA handles parallel components, while the CPU manages sequential tasks in the same System -on-Chip (SoC). Using PolarFire Icicle FPGA platform, we process 20 MRI brain scan images (128x128) from the Kaggle dataset. Implementing both algorithms in parallel on the FPGA results in a 1.97x acceleration compared to a CPU -only implementation, mainly achieved by a 1973x reduction in latency when moving the Otsu algorithm from the CPU to the FPGA. This optimization employs DSP/MATH blocks, loop unrolling, and pipelining techniques.
引用
收藏
页数:5
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