A 0.35mm2 94.25μW Fully Integrated NFC Tag IC Using 0.13μm CMOS Process

An NFC tag chip employing the ISO/IEC14443-Aprotocol is developed in SMIC 0.13 mu m EEPROM 2P6M CMOS process, boasting a chip area of 620.03 mu mx567.93 mu m and a power consumption of under 100 mu W. The chip addresses critical issues such as reducing power consumption and minimizing area costs for covering numerous IoT nodes. For a small area of the chip, a specialized ESD protection circuit is proposed, efficiently multiplexing discharge transistors, cross-gate connected rectifiers, limiters for overvoltage protection, and load switch modulators within the chip's limited space. For power efficiency, a compact175.44 mu mx32.98 mu m 18.52 mu A LDO based on the current mirror and current feedback is presented for the DC supply during the100% ASK modulation. Additionally, an ASK demodulator and a13.56MHz +/- kHz clock generator are designed in compact areas of62.19 mu mx56.06 mu m and 24.76 mu mx13.14 mu m, respectively. These components ensure stable protocol communication with digital circuits and support a 7kb EEPROM, providing a comprehensive solution for NFC-based IoT information collection.