Energy-Efficient Design for Logic Circuits Using a Leakage Control Configuration in FinFET Technology

The multigate technology adopted in the latest processors is based on the Fin-shaped field effect transistor (FinFET). In the pursuit of increasing the computational power of the metal oxide semiconductor field effect transistor (MOSFET), ceaseless downscaling drove the channel length of MOSFETs to be comparable to their depletion widths around drain and source terminals. This led to a sequence of issues, which include drain-induced barrier lowering (DIBL), roll-off of threshold voltage, leakage power, hot carrier effects, mobility reduction, and an increase in reverse leakage current. The use of MOSFET was questioned at lower technology nodes because short channel effects (SCEs) lead to the loss of gate terminal command on the channel. This research work proposes a leakage power control technique based on the reverse body bias effect. The transistor configuration has been proposed to put a curb on the leakage power. The results have been approved on some fundamental logic gates and a C17 ((ISCAS-85) benchmark circuit. The shorted-gate (SG) FinFET-based proposed inverter confirms a leakage power and power delay product (PDP) reduction of 51.09% and 25.90%, respectively. The power optimization and PDP optimization of 45.47% and 49.12% have been observed in the low-power NAND gate. The proposed 2-input NOR gate depicts a leakage power and PDP mitigation by 69.60% and 70.58%, respectively. Similarly, the SG FinFET-based proposed C17 benchmark circuit shows leakage power and PDP reduction of 56.17% and 43.20%, respectively, as compared to the conventional circuit. Monte Carlo (MC) analysis is completed with a ± 10% digression in operating conditions to calculate reliability. © The Institution of Engineers (India) 2024.