Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage(BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches(DTMOS),an oxide trench between the source and drain regions,and a trench gate extended to the buried oxide(BOX). The proposed device has three merits. First,the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide( εox) than that of Si(εSi). Furthermore,the trench gate,the oxide trench,and the BOX cause multi-directional depletion,improving the electric field distribution and enhancing the RESURF(reduced surface field) effect. Both increase the BV. Second,the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third,the trench gate not only reduces the on-resistance,but also acts as a field plate to improve the BV. Additionally,the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit(HVIC),effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.