INTRINSIC JITTER OF POSITIVE ZERO NEGATIVE JUSTIFICATION SYSTEMS USING DIGITAL CLOCK RECOVERY

被引:0
|
作者
KUHNE, F
KAMP, N
机构
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:352 / 356
页数:5
相关论文
共 50 条
  • [21] Research on high-speed digital optical signal jitter measurement technology based on clock recovery algorithm using eye diagram opening area
    Liu, Suping
    HELIYON, 2024, 10 (15)
  • [22] Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection
    Chang, HH
    Yang, RJ
    Liu, SI
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (12) : 2356 - 2364
  • [23] Alternative Reduction by Stages of Keplerian Systems. Positive, Negative, and Zero Energy
    Crespo, Francisco
    Ferrer, Sebastian
    SIAM JOURNAL ON APPLIED DYNAMICAL SYSTEMS, 2020, 19 (02): : 1525 - 1539
  • [24] 155-mb/s burst-mode clock recovery circuit using the jitter reduction technique
    Hwang, JS
    Park, CS
    Park, CS
    IEICE TRANSACTIONS ON COMMUNICATIONS, 2003, E86B (04) : 1423 - 1426
  • [25] A 20-Gbps Low Jitter Analog Clock Recovery Circuit for Ultra-Wide Band Radio Systems
    Hamouda, M.
    Fischer, G.
    Weigel, R.
    Baenisch, A.
    Ussmueller, T.
    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 1516 - 1519
  • [26] Clock and data recovery circuit using digital phase aligner and phase interpolator
    Lee, Seung-Woo
    Seong, Chang-Kyung
    Choi, Woo-Young
    Lee, Bhum-Cheol
    IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,, 2006, : 690 - +
  • [27] Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter
    Su, Yung-Chuan
    Huang, Shi-Yu
    2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2022, : 45 - 46
  • [28] Transient bit error rate analysis of data recovery systems using jitter models
    Tang, YH
    Geiger, RL
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, 2002, : 185 - 188
  • [29] Ultralow timing jitter 40-Gb/s clock recovery using a self-starting optoelectronic oscillator
    Lasri, J
    Devgan, P
    Tang, RY
    Kumar, P
    IEEE PHOTONICS TECHNOLOGY LETTERS, 2004, 16 (01) : 263 - 265
  • [30] A 1.08-Gb/s Burst-Mode Clock and Data Recovery Circuit Using the Jitter Reduction Technique
    You, Kae-Dyi
    Chiueh, Herming
    ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 1899 - 1902