OPTIMAL ALGORITHM FOR TESTING STUCK-AT FAULTS IN RANDOM-ACCESS MEMORIES

被引:0
|
作者
KNAIZUK, J
HARTMANN, CRP
机构
[1] SUNY COLL OSWEGO,DEPT COMP SCI,OSWEGO,NY 13126
[2] SYRACUSE UNIV,SCH COMP & INFORMAT SCI,SYRACUSE,NY 13210
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
引用
收藏
页码:1141 / 1144
页数:4
相关论文
共 50 条
  • [31] TECHNOLOGY AND LAYOUT-RELATED TESTING OF STATIC RANDOM-ACCESS MEMORIES
    CHAKRABORTY, K
    MAZUMDER, P
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1994, 5 (04): : 347 - 365
  • [32] TEST PROCEDURES FOR A CLASS OF PATTERN-SENSITIVE FAULTS IN SEMICONDUCTOR RANDOM-ACCESS MEMORIES
    SUK, DS
    REDDY, SM
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1980, 29 (06) : 419 - 429
  • [33] On-line Testing of Coexistent Stuck-at and Open Faults in NoC Interconnects
    Bhowmik, Biswajit
    Biswas, Santosh
    Deka, Jantindra Kumar
    [J]. PROCEEDINGS OF THE 2016 IEEE REGION 10 CONFERENCE (TENCON), 2016, : 157 - 162
  • [34] Pseudo-exhaustive Testing of Sequential Circuits for Multiple Stuck-at Faults
    Matrosova, A.
    Mitrofanov, E.
    [J]. PROCEEDINGS OF 2016 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS), 2016,
  • [35] Testing Multiple Stuck-at Faults of ROBDD Based Combinational Circuit Design
    Shah, Toral
    Matrosova, Anzhela
    Kumar, Binod
    Fujita, Masahiro
    Singh, Virendra
    [J]. 2017 18TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS 2017), 2017,
  • [36] Neural network model for testing stuck-at and delay faults in digital circuit
    Pan, ZL
    [J]. 17TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: DESIGN METHODOLOGIES FOR THE GIGASCALE ERA, 2004, : 499 - 504
  • [37] LINEAR SUM CODES FOR RANDOM-ACCESS MEMORIES
    FUJA, T
    HEEGARD, C
    GOODMAN, R
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (09) : 1030 - 1042
  • [38] Halide perovskites for resistive random-access memories
    Kim, Hyojung
    Han, Ji Su
    Kim, Sun Gil
    Kim, Soo Young
    Jang, Ho Won
    [J]. JOURNAL OF MATERIALS CHEMISTRY C, 2019, 7 (18) : 5226 - 5234
  • [39] Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories
    Cheng, KL
    Tsai, MF
    Wu, CW
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2002, 21 (11) : 1328 - 1336
  • [40] LOCALIZATION OF FAULTS IN RANDOM-ACCESS MEMORY DEVICES
    GAVRILOV, AA
    [J]. AVTOMATIKA I VYCHISLITELNAYA TEKHNIKA, 1980, (02): : 61 - 65