High Frequency Electrical Characterization of 3D Signal/Ground through Silicon Vias

被引：3

作者：

Adamshick, Steve ^{[1
]}

Carroll, Robert ^{[1
]}

Rao, Megha ^{[1
]}

La Tulipe, Douglas ^{[1
]}

Kruger, Seth ^{[1
]}

Burke, John ^{[2
]}

Liehr, Michael ^{[1
]}

机构：

[1] SUNY Albany, Coll Nanoscale Sci & Engn, Albany, NY 12203 USA

[2] Western New England Univ, Springfield, MA 01119 USA

来源：

PROGRESS IN ELECTROMAGNETICS RESEARCH LETTERS | 2014年 / 47卷

关键词：

Energy efficiency - Integrated circuit interconnects - Three dimensional integrated circuits - Silicon - Chip scale packages;

D O I：

10.2528/PIERL14052704

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

3D integration using through-silicon-vias (TSVs) is gaining considerable attention due to its superior packaging efficiency resulting in higher functionality, improved performance and a reduction in power consumption. In order to implement 3D chip designs with TSV technology, robust TSV electrical models are required. Specifically, due to the increase of signal speeds into the gigahertz (GHz) spectrum, a high frequency electrical characterization best describes TSV behavior. In this letter, 5 x 50 mu m TSVs are manufactured using a via-mid integration scheme and characterized using S-parameters up to 65 GHz. At 50 GHz, the measured attenuation constant is 0.35 dB/via with a time delay of 0.7 ps/via.

引用

页码：71 / 75

页数：5

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