OPTIMAL SCHEDULING OF SIGNATURE ANALYSIS FOR VLSI TESTING

被引：5
|
作者：
LEE, YH [1 ]
KRISHNA, CM [1 ]
机构：
[1] UNIV MASSACHUSETTS,DEPT ELECT & COMP ENGN,AMHERST,MA 01003
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1991年 / 40卷 / 03期
关键词：
SELF-TESTING; SIGNATURE ANALYSIS; TEST OPTIMIZATION; VLSI TESTING;
D O I：
10.1109/12.76412
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Signature analysis has become a popular way of testing VLSI circuits. We present a simple algorithm to optimally schedule the signature analyses. The objective is to minimize the mean testing time per VLSI circuit.
引用
收藏
页码：336 / 341
页数：6
相关论文
共 50 条
  • [41] Fuzzy logic and VLSI testing
    Atre, MV
    Kumar, DK
    DEFENCE SCIENCE JOURNAL, 1995, 45 (04) : 325 - 332
  • [42] TESTING - A MAJOR CONCERN FOR VLSI
    GRAF, MC
    SOLID STATE TECHNOLOGY, 1984, 27 (01) : 101 - 108
  • [43] VLSI TESTING ENVELOPS DESIGNERS
    不详
    ELECTRONIC DESIGN, 1986, 34 (12) : 3 - 3
  • [44] Testing VLSI regular arrays
    Univ Coll, Cork, Ireland
    J Electron Test Theory Appl JETTA, 2 (153-177):
  • [45] VLSI COMPLEXITY CHALLENGES TESTING
    BURSKY, D
    ELECTRONIC DESIGN, 1987, 35 (07) : 39 - 40
  • [46] VLSI testing - Special issue
    Das, SR
    VLSI DESIGN, 1996, 4 (03) : R1 - R4
  • [47] Special issue - VLSI testing
    Das, SR
    VLSI DESIGN, 2001, 12 (04) : I - III
  • [48] Rectangle Placement for VLSI Testing
    Aharoni, Merav
    Boni, Odellia
    Freund, Ari
    Goren, Lidor
    Ibraheem, Wesam
    Segev, Tamir
    INTEGRATION OF AI AND OR TECHNIQUES IN CONSTRAINT PROGRAMMING, 2015, 9075 : 18 - 30
  • [49] TESTING VLSI REGULAR ARRAYS
    MARNANE, WP
    MOORE, WR
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1995, 6 (02): : 153 - 177
  • [50] Testing the printability of VLSI layouts
    Martins, R
    Kirchauer, H
    14TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2001, : 186 - 191
12345