THE CHAOS ROUTER CHIP - DESIGN AND IMPLEMENTATION OF AN ADAPTIVE ROUTER

Chaotic routers are randomizing, non-minimal adaptive packet routers designed for use in the communication networks of parallel computers. Although adaptive routing, and, specifically, chaotic routing, has been shown to be superior to oblivious routing in most cases, the practical application of adaptive routing to multi-computer networks has been difficult to achieve due to the complex nature of adaptive routers. A prototype two-dimensional (mesh and torus) chaotic router chip has been designed and is being fabricated in a 1.2 mu m CMOS process. The chip exhibits high bandwidth, limited only by the speed of the off-chip drivers, and low input-to-input latency. To achieve this, much attention is given to reducing the critical path complexity of the router. The resulting chip is shown to be as good or better than state-of-the-art oblivious routers in almost all cases.