A SYNCHRONOUS DRAM WITH NEW HIGH-SPEED I/O LINES METHOD FOR THE MULTIMEDIA AGE

被引：0
|
作者：
SAKAI, Y
OISHI, K
MATSUMOTO, M
WADA, S
SAKASHITA, T
KATAYAMA, M
机构：
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 1995年 / E78C卷 / 07期
关键词：
DRAM; SYNCHRONOUS OPERATION; MEMORY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As microprocessor units have become faster, DRAMs have also been required to become faster. One of the fast DRAMs is the synchronous DRAM, which transfers data at a high rate. We have developed a 100-MHz Synchronous DRAM using pipeline architecture and new high speed I/O lines method. This paper describes some features of this DRAM and its new pipeline architecture.
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收藏
页码：782 / 788
页数：7
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