HIGH-SPEED CMOS I/O BUFFER CIRCUITS

被引：0
|
作者：
ISHIBE, M
OTAKA, S
TAKEDA, J
TANAKA, S
TOYOSHIMA, Y
TAKATSUKA, S
SHIMIZU, S
机构：
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 1992年 / E75C卷 / 04期
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D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Very high-speed off-chip data rates have been difficult to achieve in CMOS technologies. This paper describes an all-CMOS set of I/0 buffer circuits, which use current-mode and impedance matching techniques, capable of transmitting off-chip at 1-Gb/s data rates. The circuits are also compatible with voltage-mode signal levels for ECL input and CMOS output circuits.
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页码：569 / 571
页数：3
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