A NEW METHODOLOGY FOR DESIGN OF BICMOS GATES AND COMPARISON WITH CMOS

A gate comparison methodology is presented to accurately compare the performance of an arbitrary BiCMOS logic gate with a pure CMOS gate. The concept of the sizing plane is introduced, which is a geometrical framework for representation of all possible sizing choices of BiCMOS and multistage CMOS inverters in a given technology. The methodology is translated to geometrical operations in the sizing plane. This serves to highlight the important considerations in making gate comparisons. The methodology is demonstrated by fabrication in a 2-mu-m BiCMOS technology. The measured delay comparison shows that CMOS suffers larger gate delays than BiCMOS, especially for large loads, but not by as large a factor as would be obtained by previous delay comparison methods. The sizing plane helps in providing insight into the delay trends observed. The sizing plane is also shown to be a powerful tool for BiCMOS gate design where several design constraints can be simultaneously visualized and tradeoffs can be evaluated. The design procedure for some specific design criteria is demonstrated for gates in a 1-mu-m conventional BiCMOS technology. Finally, a technology comparison methodology is proposed to obtain a ratio of gate delay of BiCMOS over CMOS that is relatively constant independent of sizing dependencies. The methodology is demonstrated for a 0.6-mu-m BiCMOS technology. It is shown that a size-independent delay ratio of 0.7 is obtained for large fanout loads. For light loads, the CMOS gate is superior to BiCMOS upto a fanout of 3.