Impact of High-kappa Spacer on Junctionless Transistor in Sub-Threshold Regime

被引:1
|
作者
Ghosh, Bahniman [1 ,2 ]
Mondal, Partha [2 ]
Akram, M. W. [2 ]
Bal, Punyasloka [2 ]
机构
[1] Univ Texas Austin, Microelect Res Ctr, Austin, TX 78758 USA
[2] Indian Inst Technol Kanpur, Dept Elect Engn, Kanpur 208016, Uttar Pradesh, India
关键词
Junctionless Transistors (JLTs); Band-to-Band Tunneling (BTBT); High-kappa Spacers;
D O I
10.1166/jolpe.2014.1312
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We investigated the impact of high-kappa spacers on the off-state leakage current due to band-to-band tunneling (BTBT) in junctionless transistors (JLTs). In off-state, a significant band overlap between valence band of channel region and conduction band of drain region triggers the electrons to tunnel from valence band of channel region to conduction band of drain region and increases the off-state leakage current. Here we show that in off-state the vertical fringing electric field through the high-kappa spacer to the device layer increases tunneling distance along tunneling path of electron and reduces tunneling leakage currents.
引用
收藏
页码:293 / 296
页数:4
相关论文
共 50 条
  • [41] High-speed sub-threshold operation of carbon nanotube interconnects
    Sathyakam, Piratla Uma
    Mallick, Partha S.
    Saxena, Anmol Ajay
    IET CIRCUITS DEVICES & SYSTEMS, 2019, 13 (04) : 526 - 533
  • [42] Ultra Low Power Full Digital Body Temperature Sensor Operating in Sub-Threshold Regime
    Wu, Yuping
    Zhang, Xuelian
    Chen, Lan
    SENSING AND IMAGING, 2015, 16 (01):
  • [43] Comparative Analysis of Adiabatic Logics in Sub-threshold Regime for Ultra-Low Power application
    Chanda, Manash
    Basak, Jeet
    Sinha, Diptansu
    Ganguli, Tanushree
    Sarkar, Chandan K.
    2016 CONFERENCE ON EMERGING DEVICES AND SMART SYSTEMS (ICEDSS), 2016, : 37 - 41
  • [44] A High Sensitivity Process Variation Sensor Utilizing Sub-threshold Operation
    Meterelliyoz, Mesut
    Song, Peilin
    Stellari, Franco
    Kulkarni, Jaydeep P.
    Roy, Kaushik
    PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2008, : 125 - +
  • [45] Double-gate pentacene thin-film transistor with improved control in sub-threshold region
    Tsamados, Dimitrios
    Cvetkovic, Nenad V.
    Sidler, Katrin
    Bhandari, Jyotshna
    Savu, Veronica
    Brugger, Juergen
    Ionescu, Adrian M.
    SOLID-STATE ELECTRONICS, 2010, 54 (09) : 1003 - 1009
  • [46] Study of temperature variation on threshold voltage and sub-threshold slope of EDC MOS transistor including quantum corrections and reduction techniques
    Das, Rinkee
    Gond, Abhishek Kumar
    Sengupta, Sarmista
    Sahani, Romio Rosan
    Pandit, Soumya
    MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2017, 23 (09): : 4221 - 4229
  • [47] Impact of different NBTI defect components on sub-threshold operation of high-k p-MOSFET
    Hussin, H.
    Soin, N.
    Hatta, S. Wan Muhamad
    Bukhori, M. F.
    4TH INTERNATIONAL CONFERENCE ON ELECTRONIC DEVICES, SYSTEMS AND APPLICATIONS 2015 (ICEDSA), 2015, 99
  • [48] A Dual-Material Gate Junctionless Transistor With High-k Spacer for Enhanced Analog Performance
    Baruah, Ratul K.
    Paily, Roy P.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (01) : 123 - 128
  • [49] High Temperature and Radiation Hard CMOS SOI Sub-threshold Voltage Reference
    Boufouss, E.
    Gerard, P.
    Simon, P.
    Francis, L. A.
    Flandre, D.
    2013 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), 2013,
  • [50] High-Robust Sub-threshold Standard Cells Using Schmitt Trigger
    Zhang Yuejun
    Han Jinliang
    Zhang Huihong
    JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY, 2021, 43 (06) : 1550 - 1558