A VOLTAGE-CONTROLLABLE LINEAR MOS TRANSCONDUCTOR USING BIAS OFFSET TECHNIQUE

被引：113
|
作者：
WANG, ZH
GUGGENBUHL, W
机构：
[1] Institute of Electronics. Department of Electrical Engineering, Swiss Federal Institute of Technology
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 01期
关键词：
D O I：
10.1109/4.50321
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
— A linear large-signal MOS transconductor is described with the gain adjustable linearly by a voltage. A perfect linear transfer characteristic is obtained by two cross-coupled differential transistor pairs operating in saturation pairwise at unequal bias, offering offset-free operation, with both differential or single-ended input and differential output. Single-ended output is achievable by use of a current mirror. The nonlinearity caused by mobility reduction, channel-length modulation, mismatch, etc. is discussed. A test circuit with transconductance of 6.25 μmho has been built with 3-μm MOS components and a linearity error of less than ± 1 percent was measured for an input voltage range from -4 to 4 V. © 1990 IEEE
引用
收藏
页码：315 / 317
页数：3
相关论文
共 50 条
  • [1] A new linear transconductor combining a source coupled pair with a transconductor using bias-offset technique
    Yamaguchi, I
    Matsumoto, F
    Izuma, M
    Noguchi, Y
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2006, E89A (02) : 369 - 376
  • [2] A highly linear low-voltage MOS transconductor
    Leuciuc, A
    Zhang, Y
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, 2002, : 735 - 738
  • [3] A high-performance CMOS bias-offset linear transconductor
    Matsumoto, Fujihiko
    Miyazawa, Toshio
    Nakamaura, Shintaro
    Noguchi, Yasuaki
    IEEJ Transactions on Electronics, Information and Systems, 2009, 129 (08) : 1518 - 1526
  • [4] Noise Analysis and Design of Low-Noise Bias-Offset MOS Transconductor
    Nakamura, Shintaro
    Matsumoto, Fujihiko
    Tongpoon, Pravit
    Noguchi, Yasuaki
    IEICE TRANSACTIONS ON ELECTRONICS, 2011, E94C (01): : 128 - 131
  • [5] Technique to improve linearity of transconductor with bias offset voltages controlling a tail current
    Yamaguchi, I
    Matsumoto, E
    Noguchi, Y
    ELECTRONICS LETTERS, 2005, 41 (21) : 1146 - 1148
  • [6] Techniques for a Low-voltage Low-power Linear MOS Transconductor
    Matsumoto, Fujihiko
    Miyazawa, Toshio
    Nakamura, Shintaro
    Noguchi, Yasuaki
    2008 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS SYSTEMS (ISPACS 2008), 2008, : 355 - 358
  • [7] A linear MOS transconductor using source degeneration and adaptive biasing
    Kuo, KC
    Leuciuc, A
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 2001, 48 (10): : 937 - 943
  • [8] TECHNIQUE FOR OFFSET VOLTAGE CANCELLATION IN MOS OPERATIONAL-AMPLIFIERS
    WONG, SL
    SALAMA, CAT
    ELECTRONICS LETTERS, 1985, 21 (09) : 389 - 390
  • [9] A linear transconductor/multiplier using a matched pair of MOS transistors and a current conveyor
    Soliman, AM
    FREQUENZ, 1996, 50 (11-12) : 292 - 293
  • [10] INTERPRETATION OF NONEQUILIBRIUM MEASUREMENTS ON MOS DEVICES USING THE LINEAR VOLTAGE RAMP TECHNIQUE
    FARAONE, L
    SIMMONS, JG
    AGARWALS, AK
    TONNER, PD
    SOLID-STATE ELECTRONICS, 1981, 24 (08) : 709 - 716
12345