THE NONUNIFORM DISTRIBUTION OF INSTRUCTION-LEVEL AND MACHINE PARALLELISM AND ITS EFFECT ON PERFORMANCE

被引：35

作者：

JOUPPI, NP ^{[1
]}

机构：

[1] STANFORD UNIV,DEPT ELECT ENGN,STANFORD,CA 94305

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1989年 / 38卷 / 12期

关键词：

D O I：

10.1109/12.40844

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：1645 / 1658

页数：14

共 50 条

[41] Special issue: Instruction-level parallelism and parallelizing compilation, part 2 - Introduction
Arvind, DK
Ebcioglu, K
Lengauer, C
Schreiber, R
INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2000, 28 (05) : 429 - 430
[42] Deep jam: Conversion of coarse-grain parallelism to instruction-level and vector parallelism for irregular applications
Carribault, P
Cohen, A
Jalby, W
PACT 2005: 14TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, 2005, : 291 - 300
[43] Special issue: Instruction-level parallelism and parallelizing - Compilation, part 1 - Introduction
Arvind, DK
Ebcioglu, K
Lengauer, C
Schreiber, R
INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2000, 28 (04) : 321 - 323
[44] Efficient exploitation of instruction-level parallelism for superscalar processors by the conjugate register file scheme
Chang, MC
Lai, FP
IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (03) : 278 - 293
[45] Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism
Brandalero, Marcelo
Beck, Antonio Carlos S.
DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, 2016, 20 (02) : 155 - 169
[46] Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units
Bhagyanath, Anoop
Schneider, Klaus
2017 17TH INTERNATIONAL CONFERENCE ON APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD), 2017, : 106 - 115
[47] A Two-Way Loop Algorithm for Exploiting Instruction-Level Parallelism in Memory System
Misra, Sanjay
Alfa, Abraham Ayegba
Adewale, Sunday Olamide
Akogbe, Michael Abogunde
Olaniyi, Mikail Olayemi
COMPUTATIONAL SCIENCE AND ITS APPLICATIONS - ICCSA 2014, PT V, 2014, 8583 : 255 - +
[48] Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism
Marcelo Brandalero
Antonio Carlos S. Beck
Design Automation for Embedded Systems, 2016, 20 : 155 - 169
[49] Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers
Xiao, Haocheng
Ainsworth, Sam
PROCEEDINGS OF THE 28TH ACM INTERNATIONAL CONFERENCE ON ARCHITECTURAL SUPPORT FOR PROGRAMMING LANGUAGES AND OPERATING SYSTEMS, VOL 2, ASPLOS 2023, 2023, : 354 - 369
[50] Exploiting thread-level and instruction-level parallelism to cluster mass spectrometry data using multicore architectures
Fahad Saeed
Jason D. Hoffert
Trairak Pisitkun
Mark A. Knepper
Network Modeling Analysis in Health Informatics and Bioinformatics, 2014, 3 (1)

← 1 2 3 4 5 →