TESTING FOR SINGLE INTERMITTENT FAILURES IN COMBINATIONAL-CIRCUITS BY MAXIMIZING THE PROBABILITY OF FAULT-DETECTION

被引：1

作者：

SAVIR, J ^{[1
]}

机构：

[1] STANFORD UNIV,CTR RELIABLE COMP,COMP SYST LAB,STANFORD,CA 94305

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1980年 / 29卷 / 05期

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：410 / 416

页数：7

共 50 条

[21] DESIGN OF COMBINATIONAL CIRCUITS WITH SIMULTANEOUS CONSTRUCTION OF A FAULT-DETECTION TEST
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[J]. IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1991, 138 (02): : 191 - 197
[29] Analysis of fault detection probability of CMOS combinational circuits and its application to signature testing
[J]. Iwasaki, Kazuhiko, 1600, (21):
[30] A STUCK FAULT MODEL FOR DYNAMIC CMOS COMBINATIONAL-CIRCUITS
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