TESTING FOR SINGLE INTERMITTENT FAILURES IN COMBINATIONAL-CIRCUITS BY MAXIMIZING THE PROBABILITY OF FAULT-DETECTION

被引：1

作者：

SAVIR, J ^{[1
]}

机构：

[1] STANFORD UNIV,CTR RELIABLE COMP,COMP SYST LAB,STANFORD,CA 94305

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1980年 / 29卷 / 05期

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：410 / 416

页数：7

共 50 条

[41] DETECTION OF FAILURES IN COMBINATIONAL DIGITAL CIRCUITS
KOHAVI, Z
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[J]. PROCEEDINGS OF THE INSTITUTION OF ELECTRICAL ENGINEERS-LONDON, 1971, 118 (05): : 643 - +
[42] FAULT-DETECTION IN BILATERAL ARRAYS OF COMBINATIONAL CELLS
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[J]. IEEE TRANSACTIONS ON COMPUTERS, 1978, 27 (12) : 1206 - 1213
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[J]. IEEE TRANSACTIONS ON COMPUTERS, 1979, 28 (10) : 804 - 805
[44] PRACTICAL APPROACH TO FAULT-DETECTION IN COMBINATIONAL NETWORKS
TZIDON, A
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[J]. IEEE TRANSACTIONS ON COMPUTERS, 1978, 27 (10) : 968 - 971
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[47] ABOUT RANDOM FAULT-DETECTION OF COMBINATIONAL NETWORKS
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[J]. IEEE TRANSACTIONS ON COMPUTERS, 1976, 25 (06) : 659 - 664
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ISHIURA, N
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[50] TESTING FOR INTERMITTENT FAILURES IN COMBINATIONAL CIRCUITS BY MINIMIZING THE MEAN TESTING TIME FOR A GIVEN TEST QUALITY.
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[J]. IAHS-AISH Publication (International Association of Hydrological Sciences-Association Internationale des Sciences Hydrologiques), 1978, : 155 - 161

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