TESTING FOR SINGLE INTERMITTENT FAILURES IN COMBINATIONAL-CIRCUITS BY MAXIMIZING THE PROBABILITY OF FAULT-DETECTION

被引：1

作者：

SAVIR, J ^{[1
]}

机构：

[1] STANFORD UNIV,CTR RELIABLE COMP,COMP SYST LAB,STANFORD,CA 94305

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1980年 / 29卷 / 05期

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：410 / 416

页数：7

共 50 条

[1] A FAULT-DETECTION TEST FOR COMBINATIONAL-CIRCUITS
DANILOV, VV
TYAZHEV, VT
[J]. AUTOMATION AND REMOTE CONTROL, 1981, 42 (08) : 1117 - 1122
[2] FAULT-DETECTION IN COMBINATIONAL-CIRCUITS USING A COMPRESSED FAULT TABLE
SETHI, IK
[J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 1980, 49 (04) : 279 - 286
[3] A COMPUTER-AIDED TECHNIQUE FOR FAULT-DETECTION IN COMBINATIONAL-CIRCUITS
RAI, S
JAIN, R
[J]. MICROELECTRONICS AND RELIABILITY, 1987, 27 (02): : 263 - 265
[4] A SIMPLE RANDOM TEST PROCEDURE FOR DETECTION OF SINGLE INTERMITTENT FAULT IN COMBINATIONAL-CIRCUITS
VIRUPAKSHIA, AR
REDDY, VCVP
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1983, 32 (06) : 594 - 597
[5] ON DELAY FAULT TESTING IN COMBINATIONAL-CIRCUITS
ANTREICH, KJ
FUCHS, K
FINK, F
[J]. FREQUENZ, 1990, 44 (3-4) : 103 - 111
[6] FAULT-DETECTION IN COMBINATIONAL-CIRCUITS BY GENERALIZED ONE-DIMENSIONAL PATH SENSITIZING
BLUM, N
[J]. MICROPROCESSING AND MICROPROGRAMMING, 1985, 16 (2-3): : 194 - 194
[7] FAULT-DETECTION IN COMBINATIONAL-CIRCUITS USING GUNN-EFFECT LOGIC DEVICES
SALUJA, KK
LIDGEY, FJ
[J]. ELECTRONICS LETTERS, 1981, 17 (06) : 222 - 223
[8] IMPLEMENTATION OF FAULT SIMULATION AND TESTING OF COMBINATIONAL-CIRCUITS
MITRA, S
SAHA, B
[J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 1989, 66 (05) : 665 - 678
[9] SELF-PARITY COMBINATIONAL-CIRCUITS FOR SELF-TESTING, CONCURRENT FAULT-DETECTION AND PARITY SCAN DESIGN
GOSSEL, M
SOGOMONYAN, ES
[J]. VLSI 93, 1994, 42 : 103 - 111
[10] A PARTITIONING TECHNIQUE FOR REDUCING THE COMPUTATIONAL-COMPLEXITY OF PROBABILISTIC FAULT-DETECTION IN GENERAL COMBINATIONAL-CIRCUITS
ALI, SA
[J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 1992, 73 (06) : 1301 - 1319

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