A PARTITIONING TECHNIQUE FOR REDUCING THE COMPUTATIONAL-COMPLEXITY OF PROBABILISTIC FAULT-DETECTION IN GENERAL COMBINATIONAL-CIRCUITS

This paper examines the impacts of different types of circuit partitioning on reducing the computational complexity for computing the fault detection probability, which usually grows exponentially with the number of imput lines in the given circuit. Partitioning a large combinational circuit into arbitrary subcircuits does not, in general, reduce the computational time complexity of the fault detection probability. In fact, partitioning a given circuit into general subcircuits is expected to increase the time complexity by the amount of time spent in the partition process itself. Nevertheless, it will be shown that decomposing a general combinational circuit into its modules (supergates) such that these modules constitute the basic elements of a tree circuit (network) considerably reduces the computational complexity of the fault detection probability problem. Toward this goal, two algorithms are developed. The first partitions a given circuit into maximal supergates whenever this is possible. Its computational complexity depends linearly on the number of edges (or lines) and nodes (or gates) of the circuit. The second computes the exact detection probabilities of single faults in the tree network and its computational complexity grows exponentially with the largest number of input lines in any of the network maximal supergates rather than the total number of inputs. The case of multi-output circuits is also discussed.