A 48.1 PS HEMT DCFL NAND CIRCUIT WITH A DUAL-GATE STRUCTURE

被引:1
|
作者
SUEHIRO, H
MIYATA, T
HARA, N
KURODA, S
机构
[1] Fujitsu Laboratories Ltd, Atsugi, 243-01
关键词
HEMT; NAND; DCFL; DUAL GATE;
D O I
10.1016/0038-1101(95)00040-Z
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We fabricated HEMT DCFL 2-input NAND circuits and examined their feasibility using a dual gate structure. Our HEMT had MOVPE-grown InGaP/InGaAs/GaAs pseudomorphic HEMT structures. We first investigated characteristics of the dual gate HEMT in the short gate length region and showed that HEMTs can reveal their inherent properties even in the DCFL NAND circuits. We fabricated a 2-input NAND ring oscillator with a gate length of 0.5 mu m. It successfully operated and showed a propagation delay of 48.1 ps and a power consumption of 0.235 mW per stage at a supply voltage of 0.8 V. A master-slave type divide-by-two frequency divider which consists of eight 2-input NAND gates also showed 3.14 GHz operation with a power consumption of 2 mW.
引用
收藏
页码:1717 / 1721
页数:5
相关论文
共 50 条
  • [41] Novel dual-gate high electron mobility transistor using a split-gate structure
    Collier, N.J.
    Cleaver, J.R.A.
    Applied Physics Letters, 1997, 71 (20):
  • [42] A novel dual-gate high electron mobility transistor using a split-gate structure
    Collier, NJ
    Cleaver, JRA
    APPLIED PHYSICS LETTERS, 1997, 71 (20) : 2958 - 2960
  • [43] Dual-gate self-aligned a-InGaZnO transistor model for flexible circuit applications
    De Roose, Florian
    Celiker, Hikmet
    Genoe, Jan
    Dehaene, Wim
    Myny, Kris
    2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2019, : 25 - 29
  • [44] Simulation of FDSOI-ISFET with Tunable Sensitivity by Temperature and Dual-Gate Structure
    Wang, Hanbin
    Bi, Jinshun
    Liu, Mengxin
    Han, Tingting
    ELECTRONICS, 2021, 10 (13)
  • [45] LARGE-SIGNAL EQUIVALENT-CIRCUIT MODEL OF A GAAS DUAL-GATE MESFET MIXER
    MILES, RE
    HOWES, MJ
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1985, 33 (05) : 433 - 436
  • [46] Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure
    Kim, Hyun-Min
    Kwon, Dae Woong
    Kim, Sihyun
    Lee, Kitae
    Lee, Junil
    Park, Euyhwan
    Lee, Ryoongbin
    Kim, Hyungjin
    Kim, Sangwan
    Park, Byung-Gook
    JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2018, 18 (09) : 5882 - 5886
  • [47] Improvement of Subthreshold Characteristic of Gate-Recessed AlGaN/GaN Transistors by Using Dual-Gate Structure
    Yang, Ling
    Mi, Minhan
    Hou, Bin
    Zhu, Jiejie
    Zhang, Meng
    He, Yunlong
    Lu, Yang
    Zhu, Qing
    Zhou, Xiaowei
    Lv, Ling
    Cao, Yanrong
    Ma, Xiaohua
    Hao, Yue
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (10) : 4057 - 4064
  • [48] A dual-gate and Γ-type field plate GaN base E-HEMT with high breakdown voltage on simulation investigation
    Li, Jialin
    Yin, Yian
    Zeng, Ni
    Liao, Fengbo
    Lian, Mengxiao
    Zhang, Xichen
    Zhang, Keming
    Zhang, Yong
    Li, Jingbo
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2021, 36 (09)
  • [49] An Improved Dual-Gate Compact Model for Carbon Nanotube Field Effect Transistors with a Back-Gate Effect and Circuit Implementation
    Chen, Zhifeng
    Zhang, Yuyan
    Jiang, Jianhua
    Chen, Chengying
    ELECTRONICS, 2024, 13 (03)
  • [50] An Ultrafast Discrete Protection Circuit Utilizing Multi-Functional Dual-Gate Pads of GaN HEMTs
    Hou, Ruoyu
    Lu, Juncheng
    2019 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE), 2019, : 818 - 823