ROLE OF TEST CHIPS IN COORDINATING LOGIC AND CIRCUIT-DESIGN AND LAYOUT AIDS FOR VLSI

被引:0
|
作者
BUEHLER, MG [1 ]
LINHOLM, LW [1 ]
机构
[1] NBS,WASHINGTON,DC 20234
关键词
Compilation and indexing terms; Copyright 2025 Elsevier Inc;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
INTEGRATED CIRCUITS - Very Large Scale Integration
引用
收藏
页码:68 / 74
页数:7
相关论文
共 50 条
  • [41] THE DESIGN OF THE VLSI CIRCUIT LAYOUT PART 4. SIMULATED ANNEALING, NEURAL NETWORKS
    Nagorny, Zbigniew
    Kos, Andrzej
    INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2006, 52 (04) : 697 - 727
  • [42] THE DESIGN OF THE VLSI CIRCUIT LAYOUT - PART 2. MIN-CUT ALGORITHM
    Nagorny, Zbigniew
    Kos, Andrzej
    INTERNATIONAL JOURNAL OF ELECTRONICS AND TELECOMMUNICATIONS, 2006, 52 (03) : 469 - 488
  • [43] On the role of timing masking in reliable logic circuit design
    Krishnaswamy, Smita
    Markov, Igor L.
    Hayes, John R.
    2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 924 - 929
  • [44] Analog VLSI layout design and the circuit board manufacturing of advanced image processing for artificial vision model
    Kawaguchi, Masashi
    Jimbo, Takashi
    Ishii, Naohiro
    KNOWLEDGE-BASED INTELLIGENT INFORMATION AND ENGINEERING SYSTEMS, PT 2, PROCEEDINGS, 2008, 5178 : 895 - +
  • [45] The embedded design verification test of microwave circuit modules based on specific chips
    郭荣斌
    Mingjun Liu
    Xiucai Zhao
    Lei Xia
    电子世界, 2013, (08) : 129 - 131
  • [46] OPTIMIZATION OF THE CIRCUIT-DESIGN AND PROCESS FOR LOGIC ELEMENTS AND TRANSISTOR STRUCTURES FOR VERY-HIGH-SPEED LSI BIPOLAR ICS
    BUBENNIKOV, AN
    SOVIET MICROELECTRONICS, 1984, 13 (04): : 194 - 201
  • [47] Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
    Afacan, Engin
    Lourenco, Nuno
    Martins, Ricardo
    Dundar, Gunhan
    INTEGRATION-THE VLSI JOURNAL, 2021, 77 : 113 - 130
  • [48] CUSTOM DESIGN OF A VLSI PCM-FDM TRANSMULTIPLEXER FROM SYSTEM SPECIFICATIONS TO CIRCUIT LAYOUT USING A COMPUTER-AIDED-DESIGN SYSTEM
    JAIN, R
    CATTHOOR, F
    VANHOOF, J
    DELOORE, BJS
    GOOSSENS, G
    GONCALVEZ, NF
    CLAESEN, LJM
    VANGINDERDEUREN, JKJ
    VANDEWALLE, J
    DEMAN, HJ
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (01) : 73 - 85
  • [49] CUSTOM DESIGN OF A VLSI PCM-FDM TRANSMULTIPLEXER FROM SYSTEM SPECIFICATIONS TO CIRCUIT LAYOUT USING A COMPUTER-AIDED-DESIGN SYSTEM
    JAIN, R
    CATTHOOR, F
    VANHOOF, J
    DELOORE, BJS
    GOOSSENS, G
    GONCALVEZ, NF
    CLAESEN, LJM
    VANGINDERDEUREN, JKJ
    VANDEWALLE, J
    DEMAN, HJ
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1986, 33 (02): : 183 - 195
  • [50] Device circuit co-design to reduce gate leakage current in VLSI logic circuits in nano regime
    Rana, Ashwani K.
    INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2016, 29 (03) : 487 - 500