ROLE OF TEST CHIPS IN COORDINATING LOGIC AND CIRCUIT-DESIGN AND LAYOUT AIDS FOR VLSI

被引：0

作者：

BUEHLER, MG ^{[1
]}

LINHOLM, LW ^{[1
]}

机构：

[1] NBS,WASHINGTON,DC 20234

来源：

SOLID STATE TECHNOLOGY | 1981年 / 24卷 / 09期

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

INTEGRATED CIRCUITS - Very Large Scale Integration

引用

页码：68 / 74

页数：7

共 50 条

[21] CIRCUIT-DESIGN STRUCTURAL SYNTHESIS OF ELECTRONIC LOGIC-CIRCUITS
GLORIOZOV, EL
SOVIET MICROELECTRONICS, 1981, 10 (02): : 79 - 89
[22] SWITCHING NETWORK LOGIC APPROACH TO SEQUENTIAL MOS CIRCUIT-DESIGN
WU, MY
HAJJ, IN
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1989, 8 (07) : 782 - 794
[23] A UNIFIED THEORY FOR MOS CIRCUIT-DESIGN SWITCHING NETWORK LOGIC
WU, MY
SHU, W
CHAN, SP
INTERNATIONAL JOURNAL OF ELECTRONICS, 1985, 58 (01) : 1 - 33
[24] SPECIAL ISSUE - ASYNCHRONOUS CIRCUIT-DESIGN FOR VLSI SIGNAL-PROCESSING - INTRODUCTION
OKLOBDZIJA, VG
WEI, B
JOURNAL OF VLSI SIGNAL PROCESSING, 1994, 7 (03): : 187 - 188
[25] RADIATION-TOLERANT HIGH-PERFORMANCE CMOS VLSI CIRCUIT-DESIGN
HATANO, H
DOI, K
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1985, 32 (06) : 4031 - 4035
[26] CIRCUIT ANALYSIS, LOGIC SIMULATION, AND DESIGN VERIFICATION FOR VLSI
RUEHLI, AE
DITLOW, GS
PROCEEDINGS OF THE IEEE, 1983, 71 (01) : 34 - 48
[27] CMOS combinational circuit-design method using mixed logic concepts
Kansas State Univ, Manhattan, United States
IEEE Trans Educ, 3 (266-273):
[28] SOFTWARE UNITES TEST PROGRAM-DEVELOPMENT WITH CIRCUIT-DESIGN
VANEGMOND, K
ELECTRONIC DESIGN, 1984, 32 (23) : 207 - &
[29] A CMOS COMBINATIONAL CIRCUIT-DESIGN METHOD USING MIXED LOGIC CONCEPTS
HUDSON, WB
BEASLEY, JS
STEELMAN, JE
IEEE TRANSACTIONS ON EDUCATION, 1995, 38 (03) : 266 - 273
[30] DIGITAL VLSI CIRCUIT-DESIGN AND SIMULATION OF AN ADAPTIVE RESONANCE THEORY NEURAL-NETWORK
HO, CS
LIOU, JJ
INTERNATIONAL JOURNAL OF ELECTRONICS, 1995, 79 (02) : 151 - 162

← 1 2 3 4 5 →