Lethargic Cache: A Low Leakage Direct Mapped Cache

被引：0

作者：

Mohamed, Nagm Eldin ^{[1
]}

Akaaboune, Adil ^{[2
]}

Botros, Nazeih ^{[1
]}

机构：

[1] Southern Illinois Univ, Dept ECE, Carbondale, IL 62901 USA

[2] Intel Corp, Folsom, CA 95630 USA

来源：

JOURNAL OF LOW POWER ELECTRONICS | 2007年 / 3卷 / 02期

关键词：

Gated Vdd; Stacking Effect; Very Deep Submicron (VDSM); Virtual Ground; Cache Line Index; Average Memory Access Time (AMAT);

D O I：

10.1166/jolpe.2007.122

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes special level-1 cache scheme that greatly decreases the growing leakage power proliferation in short channel cache memories based on gated supply voltage mechanism (gated-Vdd), 1 a commonly-known circuit technique used to control power supply to cache cells. The proposed scheme slashes 26% of the total leakage dissipated in a conventional baseline at the cost of marginal performance degradation and silicon die area.

引用

页码：119 / 123

页数：5

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