A 3.8NS CMOS 16X16 MULTIPLIER USING COMPLEMENTARY PASS TRANSISTOR LOGIC

被引：0
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作者：
YANO, K
YAMANAKA, T
NISHIDA, T
SAITOH, M
SHIMOHIGASHI, K
SHIMIZU, A
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来源：
PROCEEDINGS OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 1989年
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TM [电工技术]; TN [电子技术、通信技术];
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0808 ; 0809 ;
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页码：243 / 246
页数：4
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