共 50 条
- [31] A design and implementation of reconfigurable architecture for neural networks based on systolic arrays ADVANCES IN NEURAL NETWORKS - ISNN 2006, PT 3, PROCEEDINGS, 2006, 3973 : 1328 - 1333
- [32] Integrated MAC-based Systolic Arrays: Design and Performance Evaluation PROCEEDING OF THE GREAT LAKES SYMPOSIUM ON VLSI 2024, GLSVLSI 2024, 2024, : 292 - 295
- [36] Processor clustering for the design of optimal fixed-size systolic arrays International Workshop on Algorithms and Parallel VLSI Architectures, 1991,
- [39] Automatic latency-optimal design of FPGA-based systolic arrays 10TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS, 2002, : 299 - 300
- [40] THE USE OF DATA DEPENDENCE GRAPHS IN THE DESIGN OF BIT-LEVEL SYSTOLIC ARRAYS IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1990, 38 (05): : 787 - 793