A DUAL BASIS BIT-SERIAL SYSTOLIC MULTIPLIER FOR GF(2(M))

A dual basis systolic multiplier for GF(2(m)) is presented. The multiplier is made up of two types of submodule which together form a one-dimensional array comprising m of these modules. The components in this array are nearest neighbour connected, contain no feedback path and have no complex XOR tree, hence the resulting multiplier is suitable for implementation in VLSI and is easily expandible to different GF(2(m)). It is also shown how this architecture can be modified to carry out constant multiplication, an important operation in the implementation of Reed-Solomon codes, with much reduced levels of hardware complexity. A further feature of this multiplier is that it shares a common architecture with a systolic divider for GF(2(m)).