High Efficiency 2.4 GHz CMOS Two Stages Class-F Power Amplifier for Wireless Transmitters

A design of CMOS class-F power amplifier (PA) at 2.4-GHz for wireless transmitters is presented. The class-F PA design is implemented by using 0.13-mu m CMOS process. The proposed class-F PA employs cascade topology. The transistor's on resistance is decreased by designing the transistors in parallel. Therefore, the efficiency is increased. The first stage is a common-source driver stage is biased in a class-AB to provide sufficient input voltage swing for the amplifier stage, while the amplifier stage is biased in cut-off region. Therefore, the transistor can operate as a switching-mode for high efficiency. The simulation results show that the power added efficiency (PAE) of 60% is obtained at 1.3 V power supply and the PA delivers 12 dBm output power. The chip area is 0.66 mm(2).