High Efficiency 2.4 GHz CMOS Two Stages Class-F Power Amplifier for Wireless Transmitters

被引：3
|
作者：
Murad, Sohiful A. Z. [1 ]
Isa, Mohd N. Md [1 ]
Bakar, Faizah A. [1 ]
Sapawi, Rohana [2 ]
机构：
[1] Univ Malaysia Perlis, Sch Microelect Engn, Arau 02600, Perlis, Malaysia
[2] Univ Malaysia Sarawak, Fac Engn, Sarawak, Malaysia
来源：
RECENT ADVANCES IN ELECTRICAL & ELECTRONIC ENGINEERING | 2016年 / 9卷 / 01期
关键词：
Cascade; class F; power added efficiency; power amplifier; wireless; output power;
D O I：
10.2174/2352096509666151109205645
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A design of CMOS class-F power amplifier (PA) at 2.4-GHz for wireless transmitters is presented. The class-F PA design is implemented by using 0.13-mu m CMOS process. The proposed class-F PA employs cascade topology. The transistor's on resistance is decreased by designing the transistors in parallel. Therefore, the efficiency is increased. The first stage is a common-source driver stage is biased in a class-AB to provide sufficient input voltage swing for the amplifier stage, while the amplifier stage is biased in cut-off region. Therefore, the transistor can operate as a switching-mode for high efficiency. The simulation results show that the power added efficiency (PAE) of 60% is obtained at 1.3 V power supply and the PA delivers 12 dBm output power. The chip area is 0.66 mm(2).
引用
收藏
页码：63 / 67
页数：5
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