THE ELSA WAFER-SCALE INTEGRATION PROJECT

被引：1

作者：

IVEY, P

机构：

[1] Department of Electronic and Electrical Engineering, University of Sheffield, Sheffield

来源：

IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1993年 / 16卷 / 07期

关键词：

D O I：

10.1109/33.257872

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this paper we outline some of the technology, successful and unsuccessful, of part of a large European project in wafer scale integration (WSI). The work described is an attempt to build a 64 by 64 array processor on a 4-in wafer. Such a processor would have a computing power in excess of 10 billion operations per second. A test chip and a demonstration system, which achieves such a processing power, is also outlined.

引用

页码：626 / 636

页数：11

共 50 条

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