OPTIMIZATION OF ONE-BIT FULL ADDERS EMBEDDED IN REGULAR STRUCTURES

The problem of optimizing transistor sizes is studied for the one-bit nMOS full adder either isolated or embedded in a regular array. A local optimization method called the critical-path optimization method is developed. In this method, two parameters at a time are changed along the critical path until a locally optimal choice of transistor sizes is found. The critical-path optimization method uses the Univ. of Calif. at Berkeley VLSI tools and the hierarchical layout language ALLENDE developed at Princeton Univ. The details of the critical-path optimization method and power-time tradeoff curves are illustrated. The one-bit full adder embedded in a simple array multiplier is optimized. Because the optimization of the entire circuit becomes less practical when the circuit becomes larger, a method is developed that makes use of circuit regularity. It is proved that a small array of one-bit full adders, called the canonical configuration, has the same local optima as the n multiplied by n multiplier, for large n, with the criterion of minimizing the delay time T. Hence, the computation load can be greatly reduced by optimizing this canonical configuration instead of optimizing the entire circuit.