A TEST PATTERN FOR THE EVALUATION OF BIPOLAR INTEGRATED-CIRCUIT PROCESSES

被引：0

作者：

DRUM, CM ^{[1
]}

PANOUSIS, PT ^{[1
]}

机构：

[1] BELL TEL LABS INC,ALLENTOWN,PA 18103

来源：

JOURNAL OF THE ELECTROCHEMICAL SOCIETY | 1981年 / 128卷 / 03期

关键词：

D O I：

暂无

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

引用

页码：C99 / C99

页数：1

共 50 条

[1] 3 MASK BIPOLAR INTEGRATED-CIRCUIT STRUCTURE
GLINSKI, VJ
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1972, ED19 (02) : 182 - &
[2] SCALING PRINCIPLE FOR HETEROJUNCTION BIPOLAR INTEGRATED-CIRCUIT
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[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS, 1984, 23 (12): : L913 - L915
[3] INTEGRATED-CIRCUIT TEST STRUCTURES AND TEST METHODS
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[J]. SOLID STATE TECHNOLOGY, 1981, 24 (09) : 67 - 67
[4] THE USE OF ELECTRICAL TEST STRUCTURE ARRAYS FOR INTEGRATED-CIRCUIT PROCESS EVALUATION
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[J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1980, 127 (10) : 2284 - 2290
[5] DESIGN OF A BIPOLAR INTEGRATED-CIRCUIT Y-GYRATOR
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[J]. AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 1976, 30 (01): : 13 - 18
[6] A HIGH-PERFORMANCE BIPOLAR INTEGRATED-CIRCUIT PROCESS
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[J]. HEWLETT-PACKARD JOURNAL, 1982, 33 (09): : 27 - 29
[7] HETEROGENEOUS CONDUCTION PROCESSES IN INTEGRATED-CIRCUIT ENCAPSULATION
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[J]. ACS SYMPOSIUM SERIES, 1989, 407 : 321 - 336
[8] MOS-BIPOLAR MONOLITHIC INTEGRATED-CIRCUIT TECHNOLOGY
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[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1973, ED20 (03) : 239 - 244
[9] WAFER DESIGN AND CHARACTERIZATION FOR INTEGRATED-CIRCUIT PROCESSES
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[J]. ACS SYMPOSIUM SERIES, 1985, 290 : 310 - 333
[10] MICROELECTRONIC TEST CHIPS IN INTEGRATED-CIRCUIT MANUFACTURING
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[J]. SOLID STATE TECHNOLOGY, 1981, 24 (09) : 75 - 80

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