共 50 条
- [21] Effect of FPGA Circuit Implementation on Error Detection Using Logic Implication Checking 2018 21ST EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2018), 2018, : 196 - 200
- [24] MASK PATTERN ANALYZER WITH CIRCUIT CHECK DATA AND LOGIC SIMULATION OUTPUTS. 1600, IEEE (77CH1315-1 C/CAS), New York, NY
- [27] MTJ/MOS-Hybrid Logic-Circuit Design Flow for Nonvolatile Logic-in-Memory LSI 2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, : 105 - 108
- [29] Production Mask Composition Checking Flow PHOTOMASK JAPAN 2016: XXIII SYMPOSIUM ON PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY, 2016, 9984
- [30] CHECKING DFT RULES WITH A VHDL SIMULATOR COMPUTER HARDWARE DESCRIPTION LANGUAGES AND THEIR APPLICATIONS, 1993, 32 : 537 - 550