A SUBMICROMETER MEGABIT DRAM PROCESS TECHNOLOGY USING TRENCH CAPACITORS

被引：2
|
作者：
NAKAJIMA, S
MINEGISHI, K
MIURA, K
MORIE, T
KIMIZUKA, M
MANO, T
机构：
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1985年 / 20卷 / 01期
关键词：
D O I：
10.1109/JSSC.1985.1052285
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
引用
收藏
页码：130 / 136
页数：7
相关论文
共 50 条
  • [1] A SUBMICROMETER MEGABIT DRAM PROCESS TECHNOLOGY USING TRENCH CAPACITORS
    NAKAJIMA, S
    MINEGISHI, K
    MIURA, K
    MORIE, T
    KIMIZUKA, M
    MANO, T
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (02) : 210 - 216
  • [2] DEPLETION TRENCH CAPACITOR TECHNOLOGY FOR MEGABIT LEVEL MOS DRAM
    MORIE, T
    MINEGISHI, K
    NAKAJIMA, S
    IEEE ELECTRON DEVICE LETTERS, 1983, 4 (11) : 411 - 414
  • [3] TLM - A TRENCH LEAKAGE MONITOR FOR A 4 MEGABIT SPT DRAM TECHNOLOGY
    VOLDMAN, SH
    LONG, CW
    IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1991, 4 (03) : 226 - 232
  • [4] SIMS ANALYSIS OF THE 4 MEGABIT DRAM TRENCH WALL
    ZEININGER, H
    VONCRIEGERN, R
    ROHL, S
    SURFACE AND INTERFACE ANALYSIS, 1988, 12 (1-12) : 324 - 325
  • [5] Advanced DRAM capacitors using tantalum pentoxide process technology
    Thakur, RPS
    DeBoer, SJ
    AlShareef, HN
    Gealy, D
    Singh, R
    McKinley, KA
    Sandler, NP
    PROCEEDINGS OF THE SECOND INTERNATIONAL SYMPOSIUM ON LOW AND HIGH DIELECTRIC CONSTANT MATERIALS - MATERIALS SCIENCE, PROCESSING, AND RELIABILITY ISSUES, 1997, 97 (08): : 224 - 234
  • [6] GATE OXIDE QUALITY OF DRAM TRENCH CAPACITORS
    ROHL, S
    ENGELHARDT, M
    KELLNER, WU
    SCHLEMM, A
    JOURNAL DE PHYSIQUE, 1988, 49 (C-4): : 283 - 286
  • [7] A novel method to analyze the deep trench capacitors in DRAM
    Lee, J
    Huang, KH
    Lue, JL
    ISTFA 2000: PROCEEDINGS OF THE 26TH INTERNATIONAL SYMPOSIUM FOR TESTING AND FAILURE ANALYSIS, 2000, : 241 - 244
  • [8] A novel approach to inspect abnormalities on the deep trench capacitors in DRAM
    Liu, HW
    Cheng, E
    Lin, YM
    Fan, S
    Pan, K
    Lue, JL
    Characterization and Metrology for ULSI Technology 2005, 2005, 788 : 594 - 598
  • [9] A TRENCH-ISOLATED SUBMICROMETER CMOS TECHNOLOGY
    VYAS, HP
    LUTZE, RSL
    HUANG, JST
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1985, 32 (05) : 926 - 931
  • [10] A 58nm trench DRAM technology
    Tran, T.
    Weis, R.
    Sieck, A.
    Hecht, T.
    Aichmayr, G.
    Goldbach, M.
    Wang, P. -F.
    Thies, A.
    Wedler, G.
    Nuetzel, J.
    Wu, D.
    Eckl, C.
    Duschl, R.
    Kuo, T. -M.
    Chiang, Y. -T.
    Mueller, W.
    2006 INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2006, : 322 - +
12345