Towards a Design Space Exploration Methodology for System-on-Chip

被引：0

作者：

Chariete, A. ^{[1
]}

Bakhouya, M. ^{[2
]}

Gaber, J. ^{[1
]}

Wack, M. ^{[1
]}

机构：

[1] Univ Technol Belfort Montbeliard, Rue Thierry Mieg, F-90010 Belfort, France

[2] Int Univ Rabat, Sala El Jadida 11100, Morocco

来源：

CYBERNETICS AND INFORMATION TECHNOLOGIES | 2014年 / 14卷 / 01期

关键词：

System-on-Chip; On-chip interconnect; simulation; performance evaluation; design-space exploration;

D O I：

10.2478/cait-2014-0008

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper provides an overview of a design space exploration methodology for customizing or tuning a candidate OCI architecture, given a resources budget and independent of a particular application traffic pattern. Three main approaches are introduced. The first approach allows customizing the OnChip Interconnect by adding strategic long-rang links, while the second consists in customizing the buffer sizes at each switch according to the traffic. The third approach uses a feedback control-based mechanism for dynamic congestion avoidance. Some results are presented to shed more light on the usefulness of these approaches for System-on-Chip design.

引用

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页码：101 / 111

页数：11

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