Ultra-low-voltage-trigger thyristor for on-chip ESD protection without extra process cost

被引：1

作者：

Shan Yi ^{[1
,2
]}

He Jun ^{[2
]}

Huang Wenyi ^{[2
]}

机构：

[1] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, Shanghai 200050, Peoples R China

[2] Grace Semicond Mfg Corp, Shanghai 201203, Peoples R China

来源：

JOURNAL OF SEMICONDUCTORS | 2009年 / 30卷 / 07期

关键词：

thyristor; electro-static discharge; ultra-low-voltage-trigger; positive; negative;

D O I：

10.1088/1674-4926/30/7/074010

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

A new thyristor is proposed and realized in the foundry's 0.18-mu m CMOS process for electrostatic discharge (ESD) protection. Without extra mask layers or process steps, the new ultra-low-voltage-trigger thyristor (ULVT thyristor) has a trigger voltage as low as 6.7 V and an ESD robustness exceeding 50 m Lambda/mu m, which enables effective ESD protection. Compared with the traditional medium-voltage-trigger thyristor (MVT thyristor), the new structure not only has a lower trigger voltage, but can also provide better ESD protection under both positive and negative ESD zapping conditions.

引用

页数：3

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