An on-chip NMOS ESD protection circuit with low trigger voltage and high ESD robustness

被引：0

作者：

Chen, Di-Ping ^{[1
]}

Liu, Xing ^{[1
]}

He, Long ^{[1
]}

Chen, Si-Yuan ^{[1
]}

机构：

[1] School of Physics and Microelectronics, Hunan Univ, Changsha,Hunan,410082, China

来源：

Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences | / 2卷 / 115-118期

关键词：

Deep-submicron circuits - Discharge capacities - ESD protection circuit - Gate coupling - Protection structure - Secondary breakdown - Substratetrigger - Voltage clamping;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

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