THE FLOATING-GATE MOS DEVICE AS AN ANALOG TRIMMING ELEMENT

This paper investigates the use of floating gate MOS devices for analogue trimming. A floating gate MOSFET structure, in which tunnelling occurs at the corners of a polysilicon slab, has been fabricated using a standard 1.21 mu m n-well CMOS process. A three-dimensional device simulator, DAVINCI, is used to characterize the held enhancement due to geometry. The analogue storage performance of the floating gate is evaluated. The charge-transfer behaviour of floating gate MOS devices is analysed and modelled. This model describes the charging and discharging of the floating gate, and provides insights to the design of analogue floating gate devices. A feedback-based programming strategy is also discussed.