TERNARY DYNAMIC DIFFERENTIAL NO-RACE LOGIC

A digital dynamic switching technique for CMOS that can realize ternary functions is introduced. Besides the ease of the design of the switching functions, the positive properties of a low capacitive load, a high noise margin and the need for a standard CMOS process technology should be emphasized. Furthermore, no buffering between cascaded gates is necessary. The effectiveness of the ternary switching technology in contrast to a binary one is demonstrated by the example of an array multiplier.