A COMPARATIVE-ANALYSIS OF CACHE MEMORY ARCHITECTURES FOR THE MULTIPLUS MULTIPROCESSOR

被引：0

作者：

MESLIN, AM ^{[1
]}

PACHECO, AC ^{[1
]}

AUDE, JS ^{[1
]}

机构：

[1] UNIV FED RIO DEJANEIRO,BR-20001 RIO DE JANEIRO,BRAZIL

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1992年 / 35卷 / 1-5期

关键词：

D O I：

10.1016/0165-6074(92)90368-H

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper analyses some design alternatives for the MULTIPLUS cache memory subsystem architecture. MULTIPLUS is a high performance multiprocessor system under development at NCE/UFRJ. The analysis is carried out using a simulator which supports different cache configurations. The simulator experiments have been done under three different situations: a non-cache system and the use of write back and write through control policies. The graphical results show the system behaviour in relation to the average ratio of bus occupation and the average processor cycle length.

引用

页码：555 / 562

页数：8

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