JUNCTION FORMATION AND POLY-SI DOPING FOR SCALED SUBMICRON CMOS TECHNOLOGY

The scaling of p+ and n+ junctions from 1-mu-m technology down to 0.25-mu-m technology has been examined. Dopant profiles and sheet resistances were measured as a function of rapid thermal annealing temperature over the range of 650-1050-degrees-C for 8 and 10 keV BF2, 8 and 10 keV B, and 10-50 keV As implanted single- and poly-crystalline silicon. For the shallowest junctions (<100 nm), preamorphization with either silicon or germanium did not result in shallower junctions. Although the as-implanted dopant profiles were shallower in preamorphized samples, the subsequent dopant motion during RTA was greater than that for implants into single crystal substrates so that the dopant profiles after RTA were nearly the same for both cases. Preamorphization did, however, give low sheet resistance junctions and high dopant activation at low (550-degrees-C) annealing temperatures. Considerable dopant motion (approximately 50 nm) was observed in the tail region, near the junction, after 10 s of annealing at a relatively low temperature (800-degrees-C). Annealing for 10 s up to 1000-degrees-C resulted in very little additional change in the profiles; only at 1050-degrees-C did the high concentration, shoulder region of the profile start to move. The sheet resistance of implanted poly-Si was a factor of 10-20X higher than that of single crystal Si for these shallow junction processes and was unsuitable for MOS gate applications.