The Hardware Design of Parameter-Adjustable FIR Filter System

被引：0
|
作者：
Xu, Guosheng [1 ]
机构：
[1] Weifang Univ, Weifang 261061, Peoples R China
来源：
JOURNAL OF COMPUTERS | 2013年 / 8卷 / 05期
关键词：
finite impulse response digital filter; reconfigurable coefficient; hardware design;
D O I：
10.4304/jcp.8.5.1371-1375
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
This design using FPGA parallel architecture, high computing speed and high-speed reliability of USB2.0 interface, designed an FPGA + USB2.0 + computer FIR digital filter system, organically combining the speed of FPGA and flexibility of Computer through USB2.0 bus. The results demonstrated that the coefficients configuring of the system is easy, which can adjust the filter coefficients flexibly according to the actual demand, that it can effectively filter out the noise signals.
引用
收藏
页码：1371 / 1375
页数：5
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