The Hardware Design of Parameter-Adjustable FIR Filter System

被引：0
|
作者：
Xu, Guosheng [1 ]
机构：
[1] Weifang Univ, Weifang 261061, Peoples R China
来源：
JOURNAL OF COMPUTERS | 2013年 / 8卷 / 05期
关键词：
finite impulse response digital filter; reconfigurable coefficient; hardware design;
D O I：
10.4304/jcp.8.5.1371-1375
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
This design using FPGA parallel architecture, high computing speed and high-speed reliability of USB2.0 interface, designed an FPGA + USB2.0 + computer FIR digital filter system, organically combining the speed of FPGA and flexibility of Computer through USB2.0 bus. The results demonstrated that the coefficients configuring of the system is easy, which can adjust the filter coefficients flexibly according to the actual demand, that it can effectively filter out the noise signals.
引用
收藏
页码：1371 / 1375
页数：5
相关论文
共 50 条
  • [41] A new method in FIR filter design
    Oraintara, S
    Nguyen, TQ
    [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3: ANALOG AND DIGITAL SIGNAL PROCESSING, 1999, : 275 - 278
  • [42] ON PREFILTERS FOR DIGITAL FIR FILTER DESIGN
    VAIDYANATHAN, PP
    BEITMAN, G
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1985, 32 (05): : 494 - 499
  • [43] ON FINITE WORDLENGTH FIR FILTER DESIGN
    MUNSON, DC
    [J]. IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1981, 29 (02): : 329 - 329
  • [44] Successive Approximation FIR Filter Design
    Dutra, Alessandro J. S.
    Lovisolo, Lisandro
    da Silva, Eduardo A. B.
    Diniz, Paulo S. R.
    [J]. 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 149 - 152
  • [45] Optimal design of multiplierless FIR filter
    Fang, J
    Yi, T
    Hong, ZL
    [J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 848 - 851
  • [46] Design of FIR Filter Based on FPGA
    Liu, Cai-hong
    Tian, Shuang-liang
    Liu, Zi-long
    [J]. 2018 INTERNATIONAL CONFERENCE ON SENSORS, SIGNAL AND IMAGE PROCESSING (SSIP 2018), 2018, : 46 - 50
  • [47] Low Power Design for FIR Filter
    Xu, Gaowei
    Zou, Yao
    Han, Jun
    Zeng, Xiaoyang
    [J]. 2013 IEEE 10TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2013,
  • [48] Design of FIR filter based on FPGA
    Sun Chao
    Qi Hui
    Su Tong
    Ma Junzhi
    Zhu Yongjie
    Ding Jianjun
    [J]. PROCEEDINGS OF 2020 IEEE 4TH INFORMATION TECHNOLOGY, NETWORKING, ELECTRONIC AND AUTOMATION CONTROL CONFERENCE (ITNEC 2020), 2020, : 1691 - 1694
  • [49] Design of equiripple FIR interpolation filter
    Kao, Yung-An
    Chen, Chih-Wei
    [J]. 2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4: VOL 1: SIGNAL PROCESSING, 2006, : 167 - +
  • [50] Chebyshev digital FIR filter design
    Karam, LJ
    McClellan, JH
    [J]. SIGNAL PROCESSING, 1999, 76 (01) : 17 - 36
12345