Analog and RF Performance Evaluation of Dual Metal Double Gate High-k Stack (DMDG-HKS) MOSFETs

被引:0
|
作者
Gupta, Santosh K. [1 ]
Baishya, S. [2 ]
机构
[1] Motilal Nehru Natl Inst Technol Allahabad, Allahabad 211004, Uttar Pradesh, India
[2] Natl Inst Technol Silchar, Silchar 788010, Assam, India
关键词
Dual metal double gate high-k stack (DMDG-HKS); Analog operation; Short channel effects (SCES); High-k dielectric; Equivalent oxide thickness (EOT); Transition frequency;
D O I
暂无
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
Dual Metal Gate (DMG) technology was proposed to reduce the short channel effects (SCE's) of double gate MOSFETs. But, DMG alone is not enough to rectify the problem of gate tunneling current due to thinning of oxide layer with device downscaling. So, the use of high-k dielectric as gate oxide is considered to overcome the gate tunneling effect. But, high gate dielectric thickness leads to higher fringing fields leading to undesirable higher gate capacitance. So, the use of oxide stack i. e. a combination of silicon dioxide and high-k dielectric material is preferred as gate oxide. This paper presents the evaluation of the analog performance of nMOS dual metal double gate with high-k oxide stack (DMDG-HKS) MOSFETs, comparing their performance with those exhibited by dual metal double gate (DMDG) transistors and single metal double gate (SMDG) transistors of identical dimensions. The analog performance has been investigated in subthreshold regime of operation by varying the channel length, gate oxide stack and considering different analog parameters extracted from the 2-D device simulations. It has been observed that the DMDG-HKS devices offer better transconductance gm, early voltage V-a, intrinsic gain g(m)/g(d), drain conductance g(d), transconductance generation factor g(m)/I-d, transition frequency fT, etc. The variation of these analog parameters has also been investigated by changing the equivalent oxide thickness (EOT) and channel length of the DMDG-HKS transistor and has been observed that above parameters tends to improve with channel length and EOT as well.
引用
收藏
页数:8
相关论文
共 50 条
  • [1] Effect of High-k Gate Materials on Analog and RF Performance of Double Metal Double Gate (DMDG) MOSFETs
    Gupta, Santosh Kumar
    Baishya, S.
    [J]. 2013 ANNUAL IEEE INDIA CONFERENCE (INDICON), 2013,
  • [2] Analog/RF Performance Investigation of Nanoscale Gate-Underlap Single and Double Gate Silicon-On-Insulator MOSFETs with High-k Stack on Spacer
    Singh, Indra Vijay
    Alam, M. S.
    [J]. JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2015, 10 (06) : 790 - 794
  • [3] Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study
    Vadthiya Narendar
    Kalola Ankit Girdhardas
    [J]. Silicon, 2018, 10 : 2865 - 2875
  • [4] Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study
    Narendar, Vadthiya
    Girdhardas, Kalola Ankit
    [J]. SILICON, 2018, 10 (06) : 2865 - 2875
  • [5] Impact of High-K Gate Stack on Subthreshold Performance of Double-Gate (DG) MOSFETs
    Ekta Goel
    [J]. Silicon, 2022, 14 : 11539 - 11544
  • [6] Impact of High-K Gate Stack on Subthreshold Performance of Double-Gate (DG) MOSFETs
    Goel, Ekta
    [J]. SILICON, 2022, 14 (17) : 11539 - 11544
  • [7] Analog/RF Performance Evaluation of Nanoscale Non-overlap SOI MOSFETs with High-k Stack on Spacer
    Singh, Indra Vijay
    Alam, M. Shah
    [J]. 2012 5TH INTERNATIONAL CONFERENCE ON COMPUTERS AND DEVICES FOR COMMUNICATION (CODEC), 2012,
  • [8] SEMATECHo ptimizes the gate stack with dual high-k and metal gate
    不详
    [J]. SOLID STATE TECHNOLOGY, 2006, 49 (10) : 22 - 22
  • [9] Strained Si and Ge MOSFETs with high-K/metal gate stack for high mobility dual channel CMOS
    Weber, O
    Bogumilowicz, Y
    Ernst, T
    Hartmann, JM
    Ducroquet, F
    Andrieu, F
    Dupré, C
    Clavelier, L
    Le Royer, C
    Cherkashin, N
    Hytch, M
    Rouchon, D
    Dansas, H
    Papon, AM
    Carron, V
    Tabone, C
    Deleonibus, S
    [J]. IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2005, TECHNICAL DIGEST, 2005, : 143 - 146
  • [10] Drain Current Modelling of Asymmetric Junctionless Dual Material Double Gate MOSFET with High K Gate Stack for Analog and RF Performance
    Basak, Arighna
    Sarkar, Angsuman
    [J]. SILICON, 2022, 14 (01) : 75 - 86