FAULT SIMULATION AND TEST-GENERATION IN COMBINATIONAL-CIRCUITS USING ATOMIC DIGRAPHS

被引：0

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作者：

VILLAR, E

BRACHO, S

机构：

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS | 1985年 / 59卷 / 04期

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D O I：

10.1080/00207218508920717

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

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页码：461 / 470

页数：10

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