CONTROL OF THE PERFORMANCE OF POLYSILICON THIN-FILM TRANSISTOR BY HIGH-GATE-VOLTAGE STRESS

The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFT's) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases after negative high-gate-voltage stress. The experimental results indicate that Ca and Al ions or hydrogen atoms existing in the gate oxide may be able to passivate grain boundaries at the polysilicon-SiO2 interface.