CONTROL OF THE PERFORMANCE OF POLYSILICON THIN-FILM TRANSISTOR BY HIGH-GATE-VOLTAGE STRESS

被引：4

作者：

DIMITRIADIS, CA ^{[1
]}

COXON, PA ^{[1
]}

LOWE, AJ ^{[1
]}

STOEMENOS, J ^{[1
]}

ECONOMOU, NA ^{[1
]}

机构：

[1] GEC RES LABS,WEMBLEY HA9 7PP,MIDDX,ENGLAND

来源：

IEEE ELECTRON DEVICE LETTERS | 1991年 / 12卷 / 12期

关键词：

D O I：

10.1109/55.116952

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFT's) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases after negative high-gate-voltage stress. The experimental results indicate that Ca and Al ions or hydrogen atoms existing in the gate oxide may be able to passivate grain boundaries at the polysilicon-SiO2 interface.

引用

页码：676 / 678

页数：3

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