System-level parallelism and concurrency maximisation in reconfigurable computing applications

被引：0
|
作者：
El-Araby, Esam [1 ]
Taher, Mohamed [1 ]
Gaj, Kris [2 ]
El-Ghazawi, Tarek [1 ]
Caliga, David [3 ]
Alexandridis, Nikitas [1 ]
机构：
[1] George Washington Univ, Dept Elect & Comp Engn, 801 22nd St NW, Washington, DC 20052 USA
[2] George Mason Univ, Elect & Comp Engn Dept, Fairfax, VA 22030 USA
[3] SRC Comp Inc, Colorado Springs, CO 80907 USA
来源：
INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS | 2006年 / 2卷 / 1-2期
关键词：
Reconfigurable Computers (RC); Field Programmable Gate Arrays (FPGA); Direct Memory Access (DMA);
D O I：
10.1504/IJES.2006.010165
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Reconfigurable computers can leverage the synergism between conventional processors and FPGAs to provide both hardware functionalities and general-purpose computers flexibility. In a large class of applications on these platforms, the data-transfer overheads can be comparable or even greater than the useful computations which can degrade the overall performance. In this paper, we perform a theoretical and experimental study of this specific limitation. The mathematical formulation of the problem has been experimentally verified on the state-of-the-art reconfigurable platform, SRC-6E. We demonstrate and quantify the possible solution to this problem that exploits the system-level parallelism within reconfigurable machines.
引用
收藏
页码：62 / 72
页数：11
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