Exploiting system-level parallelism in the application development on a reconfigurable computer

被引：0
|
作者：
El-Araby, E [1 ]
Taher, M [1 ]
Gaj, K [1 ]
El-Ghazawi, T [1 ]
Caliga, D [1 ]
Alexandridis, N [1 ]
机构：
[1] George Washington Univ, Washington, DC 20052 USA
来源：
2003 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT), PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/FPT.2003.1275798
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Reconfigurable Computers (RCs) can leverage the synergism between conventional processors and FPGAs to provide law-level hardware functionality at the same level of programmability as general-purpose computers. In a large class of applications, the total I/O time is comparable or even greater than the computations time. As a result, the rate of the DMA transfer between the microprocessor memory and the on-board memory becomes the performance bottleneck even on RCs. In this paper, we perform a theoretical and experimental study of this specific performance limitation for the state-of-the art reconfigurable platform, SRC-6E. We demonstrate and quantify the possible solution to this problem that exploits the system-level parallelism within the reconfigurable machine.
引用
收藏
页码：443 / 446
页数：4
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