A 2-GS/s 6-bit self-calibrated flash ADC

被引：2

作者：

Zhang Youtao ^{[1
]}

Li Xiaopeng ^{[2
]}

Zhang Min ^{[2
]}

Liu Ao ^{[2
]}

Chen Chen ^{[1
]}

机构：

[1] Nanjing Elect Devices Inst, Natl Key Lab Monolith Integrated Circuits & Modul, Nanjing 210016, Jiangsu, Peoples R China

[2] Nanjing Elect Devices Inst, Nanjing 210016, Jiangsu, Peoples R China

来源：

JOURNAL OF SEMICONDUCTORS | 2010年 / 31卷 / 09期

关键词：

analog-to-digital conversion; offset averaging; flash; interpolation; calibration;

D O I：

10.1088/1674-4926/31/9/095013

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-mu m CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s

引用

页数：5

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