HAZARD-FREE ASYNCHRONOUS CIRCUIT SYNTHESIS

This paper introduces a novel perspective on the cause of hazards in a logic implementation, and investigates their relation to conditions on traversals of the underlying boolean space. Based on this perspective, we describe a procedure to ascertain whether a given state graph describing an asynchronous behavior has a hazard-free implementation, under the assumptions of safe latches and unbounded delays. Such a state graph may be derived either from a high lever specification or an intermediate level specification in the form of a signal transition graph (or STG). The deficiencies and danger of using traditional don't care assignment procedures in the logic minimization process for asynchronous circuit synthesis are explained. An algorithm is developed for achieving a hazard-free implementation or an implementation with minimal number of hazards through proper don't care assignment. The algorithm is used in conjunction with traditional logic minimization procedures for reducing logic complexity. In addition, we comment on a structural theory and syntactic rules for hazard-free implementations for a subclass of STGs.